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Senior R&D Engineer

Senior R&D Engineer
by Admin on 11-16-2022 at 11:29 am

Website Synopsys

Job responsibilities:

  • SRAM / ROM Memory Compiler development
  • Integration of Memory Compiler components to make sure all required views can be generated
  • Tiler code development and support to build Memory instance back-end views: Layout, GDSII, LVS netlist, PLEF, est.
  • Perform several types of physical and functional verification.
    • Validation and characterization of memory designs within dedicated environments
    • Functional verification and debugging using Synopsys VCS
    • Performing layout and netlist verification and tests through DRC and LVS
    • Memory compiler integration, validation, and maintenance
  • Generation of the complete set of release views and documentation.
  • The formal release of Memory Compilers and post-release support.

Key qualifications:

  • BS in Electrical Engineering or Computer Science (MS is preferable)
  • 8 years of professional related experience in the related field is highly preferred
  • Good knowledge in transistor level Digital design and layout
  • Understanding of CMOS process fabrication technology
  • Working knowledge of Synopsys design tools, and simulators (Hspice, Finesim, Waveview, Custom Designer)
  • High-level knowledge of Linux and Windows operating systems
  • Working knowledge of Verilog is a plus
  • Knowledge of Python or TCL scripting language is a plus
  • Good written and verbal English language skills
  • Good communication skills
  • Ability to quickly learn and use Memory Compiler development tools and environment.
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To view the job application please visit sjobs.brassring.com.

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