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Senior Engineer I – Layout Design

Senior Engineer I – Layout Design
by Admin on 05-28-2024 at 4:26 pm

Website Alphawave Semi

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

What you’ll do:

  • Lead layout design activity and work closely with design team.
  • Produce high quality IPs/AMS Blocks/Macros.
  • Drive Area estimation, floor planning, placement, routing, power planning, verification, EMIR, ESD-LUP verification and tape out activity.
  • Mentor Junior Analog IC Layout engineers.
  • Develop scripts.
  • You will be reporting to Manager-Layout Design

What you’ll need:

  • 5+ years of experience in Analog Layout.
  • Minimum Education requirement is bachelor’s degree in electrical engineering.
  • Understanding of low parasitic, high frequency design techniques.
  • Excellent understanding of analog layout concepts and issues.
  • Experience in handling blocks and macros layout towards successful, high-quality, and timely execution
  • Experience with Finfet process and lower nodes like 2nm/3nm/5nm/7nm in TSMC foundry.
  • Experience with multiple foundries in lower node eg: Samsung, TSMC, GF.
  • Experience with Cadence tools (Virtuoso), Synopsys (CC), Calibre and ICV verification tools like LVS, DRC, Extraction etc.
  • Experience with EMIR, PERC tools.
  • Skill/TCL scripting experience.
Apply for job

To view the job application please visit

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