Senior Engineer I – DFT
![Alphawave Semi](https://semiwiki.com/wp-content/uploads/job-manager-uploads/company_logo/2023/02/alphawave-semi-logo-150x22.png)
Website Alphawave Semi
What You’ll Do:
- To work in a fast environment with multiple HSIO IP (CXL/PCIe, DDR, HBM, UCIe) and SoC designs
- Design and implement state-of-the-art DFT architecture to meet growing industry demands for efficient test and debug capabilities.
- Generate and Insert DFT structures at the RTL and gate levels, verifying the correct operation of those structures from RTL to back-annotated gates.
- Generate scan-inserted netlists, produce ATPG patterns to achieve coverage targets, and simulate them for correctness.
- Run timing analysis, review constraints and waivers, analyze violations, and work with other teams to fix the design.
- Produce ATE test patterns for MBIST, Scan, Functional & analog testing and support silico ATE testing and debug.
- Participate in diagnostics and failure analysis for customer returns.
- Mentor and lead a team of junior engineers to accomplish all the above tasks within the defined project constraints.
- You will report to the head of the Central DFT Team.
What You’ll Need:
- Ability to think outside the box and form real-time solutions within the project constraints.
- Be a collaborative team player with a positive attitude and a deep sense of task ownership
- Experience with UNIX, Perl, TCL, and other scripting languages is a must.
- RTL and/or VHDL coding experience is highly desirable.
- Design verification experience is a plus.
- VCS/NCSim or Verilog simulator experience. Familiarity with Spyglass tool & checks
- Familiarity with DesignCompiler/DFT Compiler/TestKompress/Tessent tools/TetraMax
- Experience with Tessent MBIST or SNPS SMS compilers
- Experience with static timing analysis and PrimeTime tool
- Experience with modern DFT techniques, JTAG standards (1149/1500/1687), scan and clock control designs, and best practices for ATPG
- Understanding of general high-speed, small-tech node design techniques
Good To Have:
- Bachelor’s degree in engineering science, Electrical and Computer Engineering or Computer Science
- 4+ years of experience in the semiconductor industry in engineering or leadership roles in RTL, Verification, DFT or FE/PD capacity. Applicants with less experience may be considered for other DFT positions within the team.
- Experience with DFT EDA tools from Tessent, SNPS, and Cadence.
“Hybrid Work Environment”
As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:
- Competitive Compensation Package
- Restricted Stock Units (RSUs)
- Hybrid Working Model
- Provisions to pursue advanced education from Premium Institute, eLearning content providers
- Medical Insurance and a cohort of Wellness Benefits
- Educational Assistance
- Advance Loan Assistance
- Office lunch & Snacks Facility
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