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Senior ASIC Engineer/Digital Verification

Senior ASIC Engineer/Digital Verification
by Admin on 06-26-2023 at 4:56 pm

  • Full Time
  • San Jose, CA
  • Applications have closed

Website Movellus

We’re looking for a talented, senior level ASIC engineer to join our passionate, mission-driven, tightly-knit team. As part of the development team, you will play a critical role developing disruptive industry leading technology. You will have a variety of responsibilities and be able to apply your skills and knowledge to design and deliver key new technology that forms the backbone of Movellus IP. The Movellus team will be committed to your intellectual, technical, and professional development.

Core Responsibilities

  • Functional verification of RTL-level IP and systems
  • Working directly with application engineering to support customer engagements
  • Test coverage analysis
  • Working with silicon validation team for post-silicon analysis
  • Sign-off ownership for IP functionality
  • Prioritizing tasks and achieving milestones
  • Project planning

Desired Experience

  • Block-level and system-level Verilog verification in an ASIC environment
  • Familiarity with Verilog, UVM, System Verilog and Python
  • TCL is a plus
  • Full-flow verification (RTL, gates, gates with SDF)
  • ASIC tapeout experience
  • Familiar with coverage metrics including functional coverage
  • Use of industry standard simulation tools
  • Development of ASIC regression suites
  • Full-system performance testing
  • Use of version control systems
  • Working in a multi-person development team sharing the same codebase, comfortable with industry standard software version control systems
  • Strong communication skills and ability to work as a team player

Bonus Experience

  • RTL design
  • Design for test (DFT)
  • Working in a fast-paced startup environment
  • Working directly in customer engagements

A Bachelor’s degree in Electrical Engineering is required. MSEE preferred.

Apply at: careers@movellus.com

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