Senior ASIC Digital Verification Engineer

Job Description and Requirements

The Senior ASIC Digital Verification Engineer will specify requirements and follow through on the implementation. This is a key position delivering digital IP to the semiconductor industry.

Role Responsibilities:

• Work with the design team to define the verification requirements.
• Develop test plans from a specification document.
• Write UVM verification test bench architecture, agents, and test sequences.
• Review test plans and verification code,
• Implement SVA for functional and formal verification.
• implement coverage and review coverage results.

Required Qualifications and Experience:

• 5+ years’ relevant experience
• Experience with Verilog/System Verilog coding and simulation tools
• Experience in verification methodology (UVM).
• Understanding of one or more of protocols AMBA (AMBA2, AXI, CHI)/DDR/PCIe
• Programming skills such as C, System Verilog, TCL Perl or Python
• The ability to work autonomously, precisely, and to drive innovation
• The ability to extract detailed verification requirements from a high-level specification
• Good communication skills.