R&D Engineer, Sr I

Job Description and Requirements

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

We’re looking for a Senior R&D Engineer to join the team.

Does this sound like a good role for you?

In this role you would be working in the Designware/Datapath R&D. Work on projects in the areas of Arithmetic, Datapath synthesis and optimization, RTL high-level optimization, power optimization and physical synthesis for datapath circuits.

Responsibilities include implementing efficient algorithms and data structures as well as tuning optimization heuristics for datapath and DSP circuits used by the cutting-edge digital ICs. Expected to deliver high quality software based on robust solutions and rigorous testing.

Key Qualifications:

• Master in CS/EE/CE with 5+ years of relevant experience or a PhD with excellent research background in the synthesis, arithmetic, low-power, physical design areas.
• Experience in developing and maintaining C or C++ based applications on Unix/Linux. Skillful in using script languages such as TCL, Perl, Unix shell scripts.
• Experience with software development processes, and proficiency with debugging tools.
• Proficiency in designing data structures, algorithms, and specs for sophisticated software products.
• You must have solid communication skills, verbal and written. Ability to coordinate discussions with other R&D teams.
• Prior domain understanding in one or more of the following EDA areas:
  – Arithmetic and Datapath synthesis and optimization
  – RTL high-level optimization
  – Digital circuit power analysis and optimization
  – Digital IC design flows (ASIC and FPGA).
• Prior understanding and experience of EDA tool development and hardware design would be a BIG plus