Principal Verification Engineer
Website ArterisIP
Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
As a Principal Verification Engineer at Arteris, you will have a leading role in the development of next generation of Arteris IP solutions, enabling the design of extremely configurable digital logic blocks.
We intend to revolutionize the way to design SoC, and we are looking for engineering talents willing to expose themselves to new design and verification methodologies and ready to learn and grow his competences to both digital design verification and software development.
You will create designs and test benches in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up.
The position will be ideally staffed in Sophia Antipolis, France, as part of the advanced engineering team.
You will join a proven-successful company and be able to shape the future of System on Chip design.
Key Responsibilities:
- Lead the development of advanced test benches for validating next generation interconnect
- Coordinate your engineering team for reaching the verification objectives
- Define, document, develop, and execute RTL verification test/coverage at system level
- Performance verification and power-aware verification
- Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
- Help improve and refine verification process, methodology, and metrics
Experience Requirements / Qualifications:
Required:
- 10+ years of experience in SoC digital design & verification
- Verification flow enhancements using SW programming languages
- Strong RTL (Verilog) and UVM/C test bench debugging skills
- Experience integrating vendor provided VIPs for unit and system level verification
- Excellent problem solving, strong communication and teamwork skills,
- Self-driven, able to work with minimum supervision.
Desired:
- Experience with Arm AMBA protocols
- Experience with digital HW generators, methodology and concept.
Education Requirements:
- PhD or master’s degree in Computer Sciences or related field.
About Arteris:
Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.
With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com.
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To view the job application please visit www.arteris.com.
Reachability in Analog and AMS. Innovation in Verification