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Principal Verification Engineer

Principal Verification Engineer
by Admin on 10-11-2023 at 1:46 pm

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Verification Engineer involved in functional verification of embedded FPGA cores in different process nodes.

Responsible for all aspects of verification including:

  • Development of verification testbenches using SystemVerilog/UVM
  • Development of test plans and execution to plan and coverage goals
  • Development of coverage plans and metrics, drive coverage activities and test writing
  • Development of scripts for automation of the verification process
  • Gate-Level simulation and debug

Required Experience

  • BSEE/MSEE with at least 10+ years of relevant experience.
  • Well versed in Verilog and SystemVerilog testbench design, stimulus, and debug
  • Able to craft requirements and design specifications into test plan or verification plan documentation and execute to plan and coverage goals
  • Familiar with scripting languages such as Perl, Python, and csh for the purposes of automation and management of large parallel simulation tasks
  • Hands-on experience with standard functional simulators like Questa, NCSIM or VCS
  • Experience running and debugging gate simulations
  • Good written, in-person and remote communication skills

Desired skills:

  • Experience with DFT pattern verification and debug
  • FPGA verification experience
  • Experience with SDF-annotated gate simulations
  • Familiarity with continuous integration infrastructure such as Jenkins
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