Webinar PQC SemiwikiV4

Principal Solutions Engineer – RTL Design

Principal Solutions Engineer – RTL Design
by Admin on 07-25-2023 at 3:59 pm

Website Cadence

Cadence Solutions (North America) team is looking for an experienced RTL designer to contribute to architecture and design for next generation SoCs targeting Hyper-Scalar, Automotive, IoT and Mil-Aero markets. Please note; US Citizenship or Green Card required. Position presents a learning and growth opportunity for candidate to develop into an architect (System) in the future.


  • This Role is primarily targeted for the skills related to CDC/RDC expertise from an RTL design team perspective,
  • Candidate should have expertise in CDC/RDC cleanup and design closure w.r.t CDC/RDC for at least couple of SOCs

In addition to the above, Candidate will have following responsibilities based on each project

  • CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP
  • Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe, Ethernet, USB and other)
  • Digital design and IP creation/ownership from High Level Arch Specification
  • Create detailed Micro-architecture specification, work closely with the architect
  • Understanding of performance measurement and refinement. Ability to work with verification/validation team to create performance verification plan
  • RTL development
  • Support Verification teams. Support test bench development, review verification and vPlans. Provide timely specification clarifications and debug support
  • Physical design deliverables. Create functional timing constraints, synthesize RTL to ensure power and area targets are met and constraints are correct
  • Plan development schedule in detail and track deliverables to ensure timely IP delivery to all consumers
  • Work with multi-disciplinary teams to ensure design block/IP success for all target specifications in Silicon


  • BS/MS Electrical Engineering with 6+ years of Front End design and/or verification.
  • Experience in Synthesis, LEC and CDC/RDC tools preferred
  • Good experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
  • Expert in RTL design (Verilog), simulators debuggers
  • Experience in C/C++ and/or Python (or scripting language). Experience in driving results in multi-disciplinary organization


  • US Citizenship or Green Card
  • A Self-motivated person with good communication and design management skills
  • Experience with Cadence front end toolset

The annual salary range for San Jose, CA is $ 119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

Share this post via: