Principal Product Engineer

–  Presales technical support of customer demos and evaluations.

– 售前技术支持，为客户提供IP 产品演示和方案评估。

–  Supporting customers’ DDR SOC integration, and system integration questions.

– 支持客户在DDR  SOC 集成以及系统集成时遇到的问题。

–  Technical link between DDR R&D team and Field Application Engineers.

– 协同 DDR 研发团队和AE 团队支持客户现场的问题。

–  Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.

– 为当前和潜在的客户提供关键技术评估和支持。

– Aligned closely with corporate engineering and sales/marketing team on customer requirements improvement.

– 协同公司的研发和销售团队， 优化客户的具体方案需求。

– FPGA design for Lab Serdes protocol testing.

– 参与实验室高速serdes 协议FPGA 设计工作。

Requirements:

– 3~5 years’ experience in the IC design company.

– 3 ~5 年的 IC 设计经验

– Familiar with SOC DDR memory interface.

– 熟悉 SOC DDR 存储接口。

– FPGA/Hardware design background.

– 具有FPGA/硬件设计开发经验。

– Design or verification experience in IP or SoC chip level.

– 具有IP/SOC 芯片级的设计或验证经验。

– Familiar with System Verilog/VHDL and HDL simulators.

– 熟悉System Verilog/VHDL and HDL 仿真。

– Verification Methodology like UVM is required.

– 熟悉UVM 验证方法。

– Strong verbal and written communication skills in English.

– 具有较强的英语口语及书写能力。

– Strong teamwork skills with good human relationships.

– 较强的团队合作及沟通能力。