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Principal Physical Design Hardware Engineer

Principal Physical Design Hardware Engineer
by Admin on 11-14-2023 at 7:11 pm

Website ArterisIP


Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

Principal Physical Design Hardware Engineer with Arteris, Inc. d/b/a Arteris IP (Campbell, CA)

Research, design, develop, and test electronic components and systems for commercial use.  Support internal design team and customers with physical synthesis, floor planning and timing analysis. Characterize nodes and maintain libraries. Create and maintain synthesis methodologies for performance and area trade-off. Review design specification and product requirements. Maintain and create automation scripts for bucketing results. Maintain and create constraints for customer designs. Maintain and create SRAM wrappers. Analyze customer synthesis reports. Review customer floor plans and recommend changes. Run synthesis experiments with various options to converge the timing.

Position allows for partial remote work with direct reporting to 595 Millich Dr. Ste 200, Campbell, CA 95008 (Santa Clara County). Must live within reasonable commuting distance.

Requirements: Requires Master’s or Bachelor’s degree in Electrical Engineering, Electronic Engineering, or related. Position requires progressive, post-bachelor’s experience (5 years with Master’s or 7 years with Bachelor’s) which must include some experience in each of the following skills: ASIC/SoC backend design; Verilog; Timing constraints and STA analysis; RTL, Netlist, GDS, and STA; Synopsys and Cadence backend tools (Design Compiler, ICC2/Fusion Compiler, RTLA, Primetime,  Formality, Innovus); Automation of backend flows; SRAM compliers; LEC and LINT; TCL, Shell scripting and Perl; Bsub job handling; and Electronics and MOS transistors.

Salary: $178,000 – $240,000 / year

To Apply Mail Resume to: HR Recruiting, Arteris, 900 E. Hamilton Avenue, Ste 300, Campbell, CA 95008.

About Arteris:

Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.

With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease.  Learn more at arteris.com.

Apply for job

To view the job application please visit www.arteris.com.

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