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Principal Engineer Tapeout Engineering

Principal Engineer Tapeout Engineering
by Admin on 06-26-2020 at 9:42 am

Website GlobalFoundries

Summary of Duties:     

Responsible for Optical Proximity Correction (OPC) keyword coding, data review, wafer level qualification, and fab patterning interaction. Own critical layer-specific Optical Rule Check (ORC) and print quality version. Participate in layer-specific Mask Data Preparation (MDP) flow, qualifications, and runtime performance. Collaborate with OPC modeler, OPC recipe owner, product integration, and lithography to deliver optimal OPC solutions. Identify OPC problems and plan for early detection and systematic solutions to eliminate sources. Deliver ORC sampling plan for CFM, PWQ, FEM, and MFE wafer availability. Perform root cause analysis of printing and yield limiting hotspots using proven tools. Support layer-specific simulation, analysis, and full chip study. Support OPC software quality and performance evaluation. Prioritize, define, and execute projects to meet team yield, cycle time, and quality goals.

Position requires a Master’s degree in Electrical and Computer Engineering, Mechanical Engineering, Materials Science, Physics, or a related field, plus three (3) years of experience in the job offered or as a Design Enablement Engineer, Technology Enablement Engineer, PDK Design Engineer, CAD Systems Engineer, or related role in the semiconductor field. Alternatively, will accept a Bachelor’s degree in Electrical and Computer Engineering, Mechanical Engineering, Materials Science, Physics, or a related field plus five (5) years of experience in the job offered or as a Design Enablement Engineer, Technology Enablement Engineer, PDK Design Engineer, CAD Systems Engineer, or related role in the semiconductor field.

Requires experience with advanced EDA flows and tools, particularly place-and-route, physical verification, DRC scripting, process simulations, and verification. Requires experience in development of pattern matching based DFM applications using Cadence squish, Mentor Calibre/PM and Synopsys ICVPM. Requires programming experience in the following languages: C/C++, Java, TcL/TK, Perl, and Python. Requires software development experience both as a technical contributor and in a small- or medium-sized programmer and development teams. Requires experience in operation support systems and database administration. Requires experience in semiconductor OPC modeling and correction silicon processes in a foundry. Requires experience with advanced CMOS process and fabrication technologies and device physics. Requires experience working with statistical data analysis, simulation, programming numerical methods and technologies and optimization.

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To view the job application please visit gfoundries.taleo.net.