Principal Engineer

Blue Cheetah Analog Design Inc. is a growing, technology start-up headquartered in Sunnyvale, California. Our mission is to generate state-of-the-art in package die-to-die semiconductor IP solutions for the rapidly growing chiplet ecosystem. We accomplish this by providing high performance chiplet interface semiconductor IP to our global customers allowing them to reshape their product roadmaps to a more agile and cost effective chiplet based approach. Join our team to help usher in the chiplet era of semiconductor-based products.

We provide a professional benefits package including medical, dental, vision, 401K plan with company match as well as generous holiday & vacation leave. Join a team where your impact to the collective success will be clear and the big company politics do not exist.

• The ideal candidate should have strong Electrical Engineering fundamentals and coursework focused on digital and analog circuit design.
• Knowledge of BoW and UCIe, or similar interconnect standards.
• Experience with AXI, CHI, and PIPE interfaces is desired.
• Must have experience successfully integrating and/or designing high speed designs in an SOC and product level environment.

The candidate should demonstrate an ability to work independently on debug of complex tests and interacting with the design engineering team to arrive at resolution. The candidate should also be able to own the tasks provided to him/her and be able to track and report progress on a regular basis.
Excellent communication skills and an ability to work as part of a highly collaborative team are essential.

Primary Responsibilities:

• Develop and verify D2D link layer and advanced subsystems.
• Responsible for supporting integration / customization / verification of IP subsystems using advanced D2D PHY and subsystems.
• RTL development and validation
• Implement industry standard DFT and design verification flows
• Assist customers with gate level simulations and timing closure.
• Generate technical specifications, data sheets, and application notes.
• Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
• Support PHY and subsystem SOC integration reviews, and questions.

Position Requirements:

• M.S. Electrical/Computer Engineering (or similar degree)
• 10+ years of overall experience
• Experience working with SerDes, D2D, DDR, or similar interface IP
• Verilog RTL design and gate level verification experience
• Strong Verilog debug and problem-solving skills
• Experience in SOC design implementation, from RTL to final GDS
• Full understanding of SOC digital design methodology and tools
• Synthesis and STA experience, back-end experience is a plus
• Familiarity with industry standard DFT flows and test methodologies
• Ability to clearly communicate technical challenges
• Willing to travel to customer sites worldwide
• Strong communications skills
• Working with global (US, west coast and east coast) teams, which work in different time-zones

Equal Opportunity:

Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.