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Principal Design Engineer

Principal Design Engineer
by Admin on 12-09-2022 at 1:44 pm

  • Full Time
  • Cary, NC

Website Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Principal Mixed-Signal Verification Engineer is responsible for defining mixed-signal verification plans, models, and roadmaps and delivering complete Mixed-Signal DV solutions that address challenges across the full spectrum of diverse mixed-signal products. This also includes driving innovation across the Mixed-Signal verification flow to create efficient and accurate mixed-signal methodologies.

This ideal candidate is expected to be a mixed-signal DV expert and the hub between all engineering teams.


  • Architect, develop, champion, and implement metric-driven mixed-signal verification solutions, in the areas of: Digital/DMS/AMS testbench creation and generation
    • Automatic Model generation and testing
    • Cadence Design Systems AMS simulation flows
    • Mixed-Signal Assertions and Checkers
    • Behavioral Modeling and Model Validation Methodologies
    • Mixed-Signal VIP integration and testing
    • Mixed-Signal emulation flows and practices
  • Power intent verification including Low power states, state retention, and CPF/UPF integration
  • Push technology for mixed-signal modeling, simulation, and DV in order to improve mixed-signal verification efficiency and accuracy.
  • Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters, and custom solutions
  • Drive adoption of analog behavioral modeling methodologies for efficient mixed-signal verification
  • Develop efficient debug solutions and techniques
  • Develop an efficient and accurate full-stack mixed-signal methodology for the entire IP stack from the controller to the analog circuit.
  • Propagate mixed-signal knowledge and mentor junior engineers
  • Collaborate closely with:
    • Digital, Analog, Firmware, and Test engineers
    • Internal methodology and tool development teams, such as Virtuoso/ADE/Xcelium. PDK teams
    • Customer management and engineering support teams


  • 7-15+ Years’ experience in working with Digital and Analog mixed-signal environments and teams.
  • Must have good written and verbal cross-functional communication skills.
  • Proven experience in most of the following:
  • Creating Verification infrastructure (test-bench, environment, scripting)
  • Scripting of verification flows, design automation
  • Debugging verification test cases
  • Knowledge of existing and upcoming standards such as PCIE, USB, DDR4, etc.
  • Must be comfortable interacting across the IPG development team including the ability to understand design constraints.
  • Knowledge of multiple programming languages. C++, Python, System Verilog, and e (verification language) are a plus
  • Knowledge of Mixed-Signal Cadence tools and mixed-signal methodology is a plus
  • Knowledge of System Verilog and UVM Test environment and methods is a plus
  • Working knowledge of revision control tools such as SOS, SVN is a plus
  • Education Level: Bachelor’s Degree (MSEE Preferred)
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