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Principal Application Engineer – SW Verification

Principal Application Engineer – SW Verification
by Admin on 12-09-2022 at 1:45 pm

Website Cadence

Position Requirements:  

4-6 or above years’ experience in the following areas:

1. Design experience in Verilog/VHDL for IP or SoC chip level.
2. Verification with knowledge of System Verilog/VHDL and HDL simulators.
3. Experience of using formal verification, JasperGold experience is a plus.
4. Advanced Verification Methodology like UVM is a plus.
5. Strong verbal and written communication skills in English.
6. Strong teamwork skills with good human relationship.

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To view the job application please visit cadence.wd1.myworkdayjobs.com.

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