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Princ Engineer Design Enablement

Princ Engineer Design Enablement
by Admin on 04-23-2020 at 2:44 pm

GLOBALFOUNDRIES (GF), the world’s leading specialty foundry, announced today that it has acquired the PDK (Process Design Kit) engineering team from Smartcom Bulgaria AD in Sofia, Bulgaria. The newly acquired team will enhance GF’s scale and capabilities, while strengthening competitiveness of its specialized application solutions to further position the company for growth and value creation.

Process Design Kits are the critical interface between a company’s integrated circuit (IC) design and the fabs, which manufacture the clients chip products. Since 2015, Smartcom has supported GF’s PDK development and quality assurance for platform technologies spanning from 350nm to 12nm. Under the terms of the acquisition, GF will acquire Smartcom’s PDK development team of more than 125 employees.

With this acquisition, GF is expanding its worldwide design enablement capabilities and strengthening its European footprint. The Sofia operations build on GF’s long established Fab 1 operations in Dresden, Germany, the company’s Bump Test Facility (BTF) and the AMTC mask house, a joint venture with Toppan.

In addition to the current excellent Team, we are looking to significantly hire additional talent for the Bulgaria Team in Sofia immediately. We are looking for ….

Princ Engineer Design Enablement

Essential Responsibilities: 

The successful candidate will assume responsibility for a variety of embedded memory (SRAM, non-volatile memory) technology enablement and analysis projects and tasks.

  • Specific projects and tasks may include some or all of the following:
  • Parametric inline monitor test structure layout and verification
  • Post-sizing mask data GDS validation for product and test chip tapeout
  • Design manual update requests to reflect the latest design rules and guidelines developed for embedded memories, which involve formal documentation and change control systems
  • Extraction of memory bitcells used on products and test chips across multiple technologies to guide our technology roadmap based on customer use of our collateral
  • Correlation of spice models to silicon data for ongoing model quality assurance
  • Generation offab control limits on electrical parameters ofmemory bitcells, using the pice models to generate the limits
  • Embedded memory yield & parametric trend analysis for both technologies that are in development, and the more mature technologies already in manufacturing

Required Qualifications:

  • B.S. in Electrical Engineering or related field of study, with M.S. preferred. 1-2yrs experience preferred.
  • Good communication (written and verbal) in English language.
  • Familiarity with MOS transistor electrical characteristics, CMOS circuit basics are required, and understanding of CMOS SRAM preferred.
  • Skills should include HSPICE or equivalent circuit simulation, Cadence Virtuoso or Mentor Calibredrv layout systems, and some experience with design rule checking
  • (DRC) and Layout verification to schematic (LVS) preferred.
  • Coding experience with one or more of the following preferred: Python, Tcl, Linus shell script, C/C++, and Cadence SKILL.
  • Experience with statistical data analysis tools (JMP or similar) perferred. In-house training will be provided as needed for particular skills listed above.
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