As a GPU PD/STA engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power COREs.
Job Responsibilities include:
• Floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, • Implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification.
• Low power implementation methods, customized P&R to achieve area reduction and performance goals • Constraint development, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
• Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
• Good understanding of functional, test (DFT) mode constraints for place and route, • Work closely with RTL design, DFT, PD Implementation, Power teams to optimize Performance, Power and Area (PPA) for best PPA
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To view the job application please visit mobiveil.com.