Physical Design Flow Expert
Website Cadence
We are looking for a CAD/PDK engineer to work with the digital layout flow development team. The engineer would help to enable advanced technology nodes, support ongoing IP programs, maintain and improve Cadence internal physical design flow.
Job Responsibilities
- Automate tasks, test enhancements and bug fixes, run benchmarks
- Develop and maintain technology setup: PDK inputs, standard cells, floorplan procedures, signoff checks setup, tool settings
- Run test case designs through synthesis, place-and-route, static timing closure, power analysis, physical verification (DRC/LVS)
- Provide support to ongoing projects (questions, hands-on debugging). The candidate should be able to communicate clearly in English.
- Follow tool new features and known issues
- Participate in documentation and quality checks in prevision of new flow releases
Minimum Requirements
- Bachelor’s degree in Electrical/Electronic Engineering
- Strong interest in programming and automation
- Basic knowledge of the digital PD flow RTL->GDS
- Knowledge of the following Cadence tools (or industry equivalent): Innovus, Tempus, Voltus, PVS/Pegasus, Conformal
OR
- Bachelor’s degree in Computer Science
- Experience with scripted languages (TCL, Perl, shell, Python, etc.)
- Strong interest in digital electronics and IC design
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