- BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)
1. Knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI)
2. Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc)
3. Should have worked extensively on XTalk/SI/EM
4. Knowledge of CTS, Clock tree methodology and clock skewing.
5. Tool-specific knowledge: ICC, innovus, primetime, DC, Genus depending on the background
6. Knowledge of DRC/LVS, IR Drop, Formal Verification, and Synthesis.
7. The job would require complete ownership from netlist to GDS for blocks.
8. Should have worked on 28nm and lower technologies.
Tools: ICC or Innovus for PnR, Encounter for FloorPlan, Redhawk for IR Drop, PT/ PTSI, Calibre
The physical design of Hard Macros/Partitions.
Gate-level-Netlist to GDS, technologies varying from 28nm to 7nm.
PD activities involve:
Hard Macro floorplan/IR Drop/placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS
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