Package Simulation Engineer
Website Verisilicon
Descriptions
- Equivalent circuit model extraction for Package product (including R/L/C, S-parameter, IBIS).
- SI/PI simulation and analysis for Package product (including Chip-Package-Board co-simulation for high speed serial link interface, high speed parallel bus interface, high power supply).
- Work with package design team to optimize and signoff package design.
Requirements
- Bachelor or above in EE or Equivalent.
- Work experience and rank are not limited.
- Familiar with flow of package modeling and PI/SI analysis.
- Familiar with at least 1 of simulation tools(Sigrity, Ansys, Hyperlinks, ADS, Hspice…).
- Familiar with high speed interface(DDRn, PCIE, Serdes…).
- Familiar with at least 1 of layout tools(Cadence, Mentor…), knowledge in package layout is preferred.
- Good communication skill, fluent in both English and Chinese.
Apply for job
To view the job application please visit www.verisilicon.com.
TSMC’s First US Fab