Package Layout Engineer
Descriptions
- Package design feasibility study to provide the more competitive package solution; Co-work with R&D team to optimize and generate the Bump map and Ball map.
- Responsible for completing package designs, design rule set up and drawing review with package house, co-work with simulation engineer to achieve best package performance, work with customer/assembly house for design issue timely closure.
- Support both internal and external project on chip-package-PCB co-design tasks, including I/O planning, bump/ball assignment and package routing.
- Support simulation engineer on electrical/thermal characterization.
Requirements
- Bachelor or above in Engineering or Equivalent.
- Work experience and rank are not limited.
- Familiar with substrate-based package, good understanding on assembly/substrate process.
- Basic knowledge on high speed PI/SI design.
- Experience on chip-package-PCB co-design will be a plus.
- Good communication skill, fluent in both English and Chinese.
TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor