Lead Product Validation Engineer

Cadence digital full flow is the leading solution in worldwide, including synthesis, implementation, and signoff. Product validation team takes critical role in release cycle. As one part of global team, Brazil PV team will focus on Advance Node (below 3nm) and GAA technology.

Responsibility:

• Validate EDA software in ASIC design flow independently.
• Responsible for developing, applying, and maintaining quality standards for complex EDA software system.
• Develops and executes EDA software test plans.
• Analyzes and writes test standards and procedures.
• In charge of Customer Acceptance Test.

Requirement:

• Major in EE/CS, master with 3+ years’ experience or bachelor with 5+ years’ experience.
• The candidate should have good knowledge of HDL (Verilog preferred) and microelectronics. Knowledge of IC design flow.
• Previous experience of ASIC design (Cadence/Synopsys) is highly preferable. Experience with advanced nodes is a strong plus.
• Candidate must possess good English communication skills.
• Candidate must have demonstrated strong problem-solving skills, ability to work on large software systems.
• Highly motivated and passion to work is required. Detail focusing, performance oriented.