Lead Design Engineer

Responsibilities

– Create, review, verify and deliver high quality layout that conforms to all design requirements.
– Provide and maintain accurate schedule estimates
– Meet project milestone deadlines
– Independently debug complex design and PDK issues
– Drive and assist in project planning and design kit/methodology improvements

Skills/Experience Required:

– 5+ years’ experience in analog/mixed-signal layout
– Custom layout experience must include circuits such as ADC, DAC, and ,PLL,RX,TX, high speed Serdes layout experience is preferred.
– Familiarity with Cadence Virtuoso tool suite
– Full understanding of hierarchical planning (top down and bottom up) and integration
– Experience including one or more process nodes: 40nm, 28nm, 14nm, 16nm, 10nm, 7nm
– Strong verification and debugging skills
– Excellent communication skills and teamwork
– Proficiency with design management tools

Nice to Have:

– Chip level management from project inception through tape out
– Proficiency with Virtuoso XL schematic driven layout design flow and tools
– Proficiency with Virtuoso IC61 product generation