1198773726 EDA SemiWiki banner ads 3D IC800x100

Layout Design Engineer

Layout Design Engineer
by Admin on 07-11-2023 at 3:01 pm

Website Verisilicon


  • Design Analog/MS/RF/Foundation IP layout in various advanced CMOS processes.
  • Conduct physical verification and parasitic extraction.
  • Generate IP tape-out kits.


  • Bachelor’s or above degree in EE, device physics, or related majors.
  • Familiarity with Unix/Linux OS, and experience on Synopsys/Cadence/Mentor EDA.
  • Excellent learning ability.
  • Candidates who meet at least one of the following conditions are preferred:
  • Good at Perl, Tcl, Shell, or other scripting languages.
  • Self-motivated and a good team player. Good communication skills in both Chinese and English in either listening, speaking, reading or writing.
Apply for job

To view the job application please visit www.verisilicon.com.

Share this post via: