Jr. APE Engineer

Description

1. Advanced Chiplet and 2.5d IC CoWoS packaging technology development.

2. Flip chip, Bumping, Fan-Out package technology development.

3. New product introduction development (NTO, DOE and corner plan, yield analysis, MP window)

Requirements

1. +1 years of experience in Semiconductor Manufacturing specialized in advanced package engineering.

2. Good experience in 2.5d IC CoWoS, Fan-Out, Flip chip, Bumping wafer level packaging.

3. Good communication skills and fluency in both verbal and written English.

4. Experience working with diverse cultures.