Post Silicon Validation Engineer

Job Description
Core post silicon validation engineers are responsible for core level validation of the leading CPU products of each new Intel Core product. To bring these features and new platforms to market a Core post Sil validation engineer needs to be expert in CPU post Si debug and validation, knowledge in test generators for core level validation, involved in tasks such as developing validation plans, “Powering on” the very first system built with Intel’s latest & greatest CPU, validating product features and identifying and debugging all functional bugs. Our engineers have a great opportunity to enhance their skills in validation architecture & Design. Various validation techniques are used, such as emulation and while offering a unique Hardware-Software experience. In addition to various tools, languages and validation methodologies, engineers will develop expertise with Intel Architecture and Micro Architecture and will be deeply involved in the process of defining new Intel features. They are expected to be independent, creative, with the ability to innovate new solutions and demonstrate uncompromising quality during their work.

Qualifications:
-Engineers should possess a BSC or MSC degree in Electrical Engineering, Computer Engineering, Software Engineering or Computer Science.

– Experience in development in integrated software and/or hardware environment
– Familiarity with CPU architecture/assembly
– Experience in Emulation
– Experience in Chip logical validation concepts and methodologies

-Good communication and interaction skills among groups inside and outside of Israel

Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.