Intern – Fall 2020 – Test Chip Design Automation

GLOBALFOUNDRIES is seeking a highly skilled and motivated Testchip design automation intern to join a dynamic team of design and layout engineers. The team’s mission is to provide state-of-the-art test structures for microelectronic development in advanced nodes (45RF, 28nm, 22nm, 14 nm) located at our Austin, Texas office.

Essential Responsibilities:

The candidate must be proficient in programming or scripting, preferably be able to write efficient code in Cadence SKILL language to develop Parameterized Cell (PCell) and place & route script to generate layout. They must have a good understanding of physical layout, technology ground rules, and semiconductor processes.

The candidate must also possess excellent communication skills and the ability to work flexibly in a team environment. Using these skills to deliver projects on time and facilitate rapid progress across a diverse engineering team, including design, process, integration, characterization, and software tool engineers.

Design macros often consist of integrating discrete device macros into large padcages, custom functional designs, and running design rule checks (DRC) and other checking algorithms. This position heavily relies on the candidate’s ability to automate macro design, and to respond rapidly in a dynamic environment.

The candidate should also have skills in the following areas (or a subset of): semiconductor device layout, Cadence Virtuoso, knowledge of Linux/UNIX, SKILL programming, Perl, Python, TCL, shell scripting, Cadence, Calibre, and SVRF.

The ideal candidate would also possess self-motivation and proactive mentality to debug errors and solve problems with invention and ownership.

The candidate must be able to Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs