Front End ASIC RTL/Logic Design Engineer (Graduate Trainee)

Job Description

As a front end ASIC RTL/Logic Design Engineer, you will be responsible to define and implement the design (micro-architecture, RTL, linting, CDC, SDC, UPF/power gating) of high speed digital design in next generation 2.5D PHY interface (HBM and Die to Die) in cutting edge technology node. You will work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure. You will need to work on post Silicon debug/characterization support of the designs.

Qualifications

• BS or MS or PhD in Electronics Engineering.
• Strong in communication, leadership, investigation, problem solving and analytical skill.
• Proficiency with RTL coding using HDL languages.
• Familiarity with logic simulation and debug environments.
• Knowledge of Spyglass, Synthesis, STA, UPF, UVM, Spice and DFT.
• Knowledge scripting desirable.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera’s industry-leading FPGA technology and customer support with Intel’s world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.