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FPGA RTL Design Engineer

FPGA RTL Design Engineer
by Admin on 08-04-2023 at 2:50 pm

Requirements

  • Proven FPGA RTL design engineer with 3-8 years of experience
  • Experience in Xilinx Toolsets like ISE, Vivado, chipscope etc.,
  • Experience in porting FPGA designs from One architecture to the other
  • Hands on experience in timing closure and Validation
  • Exposure to various Xilinx FPGA architectures
  • Exposure to Telecom domain and all the layers of OSI(especially PHY layer)
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