FPGA RTL Design Engineer

Requirements

• Proven FPGA RTL design engineer with 3-8 years of experience
• Experience in Xilinx Toolsets like ISE, Vivado, chipscope etc.,
• Experience in porting FPGA designs from One architecture to the other
• Hands on experience in timing closure and Validation
• Exposure to various Xilinx FPGA architectures
• Exposure to Telecom domain and all the layers of OSI(especially PHY layer)