hip webinar automating integration workflow 800x100 (1)

Formal Verification Engineer

Formal Verification Engineer
by Admin on 05-05-2023 at 1:43 pm

Website Synopsys

Job Description and Requirements

The ideal candidate will have a background in RTL design and expertise in Formal verification.

Design expertise includes understanding Standard Specifications/micro-architecture documents, and the ability to design for low area/power. The designer should have a good knowledge of RTL coding guidelines. A hands-on knowledge of connectivity protocols like Ethernet, USB, SD-MMC, AMBA, and MIPI protocols such as CSI/ DSI/ UFS and Unipro; and working on the design and verification of such IP designs.

Formal verification expertise includes the ability to verify the micro-architecture using formal verification tools to employ the latest model checking and equivalence checking techniques. The ability to understand the design & implementation, define the verification scope, and ensure design correctness and then use advanced formal techniques to obtain full proofs, or sufficient bounded proofs, of the design while working with architects, designers, pre-silicon verification teams. The candidate must be capable of setting up or leading the formal verification effort, collecting coverage data, and communicating verification results and holes to our team.

Key Job Responsibilities:

  • The specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification objective.
  • Guide and train team members on effective usage of FV tools.
  • Develop/modify scripts to automate the verification process.
  • Review formal setups and proofs with design and verification teams.
  • Maintain and extend assertion libraries, including support for both simulation and FV.
  • Identifying key behaviors for verification of DUT and creating a verification plan.
  • Developing verification environment including environment assumptions, assertions, and cover properties in context of the verification plan.
  • Debugging RTL to identify causes of failure scenarios.

The candidate must have a Bachelors/Masters in Computer Science or EE from a reputed engineering college. A minimum 3+ years of industry experience with at least the last 2+ years on formal techniques for verification and relevant experience in one or more of the following areas:

  • Exceptional knowledge of architectures of digitial designs
  • Synthesis flow and static timing flows, Formal checking, etc. is a minimum requirement for candidates with design background
  • Good knowledge of abstraction techniques for effective verification
  • Hands-on experience with HDLs such as Verilog / System Verilog
  • Knowledge of temporal logic assertions
  • Experience with at least one Formal Verification Tool (e.g. Jasper, VC-Formal)
  • Worked on complex verification projects that used formal techniques for closure
  • Knowing USB protocol would be preferred
  • Experience of setting up and collaborating with geographically diverse cross-functional teams
  • A history of mentoring junior engineers and interns a huge plus
  • Perl/Shell scripts are a plus

In addition, the candidate will have good communication skills, will be a team player, and will have good problem-solving skills.

The candidate will be part of the Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities.

Share this post via: