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Engineer Trainee

Engineer Trainee
by Admin on 11-14-2022 at 12:27 pm

Website SmartDV

  • B.E or MTech from reputed university with 0-2 years experience.
  • Strong understanding of Digital design
  • Working experience with Verilog or VHDL or SystemVerilog
  • Experience in writing C or C++
  • Understanding of OOPS.
  • Knowledge of Perl or Python or TCL scripting languages
  • Very good academic track record
Apply for job

To view the job application please visit

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