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Engineer Trainee

Engineer Trainee
by Admin on 04-19-2022 at 3:51 pm

  • Full Time
  • US

Website SmartDV

  • B.E or MTech from reputed university with 0-2 years experience.
  • Strong understanding of Digital design
  • Working experience with Verilog or VHDL or SystemVerilog
  • Experience in writing C or C++
  • Understanding of OOPS.
  • Knowledge of Perl or Python or TCL scripting languages
  • Very good academic track record

SmartDV offers a unique opportunity for ambitious ASIC engineers. As a ASIC design and verification expert you will have range of projects to work with. You will have opportunity to work with industry’s best talent.

At SmartDV you will get to work on technologies which are very innovative and will have chance to contribute to this innovative technologies. If you think you know next big thing in verification, or you think you can solve next big issue in verification, then SmartDV is right place for you. Send your resume to

Apply for job

To view the job application please visit

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