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Digital Verification Engineer

Digital Verification Engineer
by Admin on 04-15-2024 at 2:52 pm

Blue Cheetah Analog Design

Blue Cheetah Analog Design Inc. is a growing technology start-up headquartered in Sunnyvale, California. Our mission is to generate state-of-the-art “in package” die-to-die semiconductor IP solutions for the rapidly growing chiplet ecosystem. We accomplish this by providing high performance chiplet interface semiconductor IP to our global customers, allowing them to reshape their product roadmaps to a more agile and cost effective chiplet based approach. Join our team to help usher in the chiplet era of semiconductor-based products.

We provide a professional benefits package including medical, dental, vision, 401K plan with company match as well as generous holiday & vacation leave. Join a team where your impact to the collective success will be clear and the big company politics do not exist.

Job Overview:

  • Blue Cheetah requires expertise to ensure our verification environment is highly reusable, scalable, modular and customizable across multiple interface IP’s in leading edge process nodes.

Position Details: We are looking for an individual with the knowledge and skills to accomplish any subset of the following Position Details skills.

  • Create verification test plans and execute them including assertion-based, directed and randomized tests, or
  • Create coverage metrics & reports and drive coverage goals and execution, or
  • Develop firmware tests exercise critical IP training and other functionality and support customer adoption of these tests and other SOC tests with great efficiency, or
  • Experience with Verification IP integration and/or development, or
  • Experience with a coverage-driven verification methodology from planning through closure – Knowledge of industry standard bus or I/O interfaces, or
  • Experience with SystemVerilog Assertions (SVA) – FPGA/ASIC design and/or development process experience – Experience with scripting languages (Bash, Perl, Python, Tcl, Makefile), or
  • Support gate level verification and various back-annotation methodologies, or
  • Use experience and foresight to drive automation in the verification process to achieve scale and efficiency, or
  • Support silicon bring-up and characterization including ATE vector creation etc, or
  • Formal verification, or
  • Create metrics to track verification progress

Position Requirements:

  • 8+ years’ experience in verification leading the verification of complex highspeed interface IP like DDR/Serdes/high-speed IO with proven track record of timely delivery and silicon success
  • Experience working on advanced technology nodes
  • Strong exposure to the following methodologies:

o UVM/OVM/eRM/VMM flow/methodologies

o Using VIP’s in verification flows

o BIST methodologies and verification

o Low-power design and verification techniques (UPF/CPF), low-power cell verification including isolation cells, retention cells etc.

  • Innate drive to figure out a better way to do things

PLUS Skills:

  • Protocol drivers, scoreboards, monitors, RAL models and assertions

General Requirements:

  • BS/MS/PhD in ECE/EE/CS
  • Strong exposure to the following tools/toolsets:

o C, C++, System-verilog, SVA, Verilog.

o Scripting languages like Python, Tcl, Perl, shell

o Regression scripts

o VCS, Verdi, Questa, Xcelium etc.

Equal Opportunity:

Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.


In addition to Blue Cheetah’s generous benefit package, the target base pay range for this role is between $145,000 and $225,000. Your base pay will depend on your skills, qualifications, experience, and location

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