Digital Verification Engineer

What you will be doing:

• Digital IP verification in mixed signal IP developments
• Working collaboratively with technical leaders and engineers
• Developing the digital and mixed signal verification strategy and infrastructure

What we need from you:

• Hands-on experience and a track record of using advanced verification methodologies such as: Directed testing; Constrained random testing; Assertion-based testing; OVM/UVM; and Code coverage analysis
• A working knowledge of a variety of aspects of ASIC development such as: Verilog RTL coding; Design synthesis; Timing constraints and static-timing analysis; and DFT, scan-testing, and ATPG
• Experience of leading digital EDA tools for simulation, code debug & analysis etc
• Understanding on asynchronous clock domains & multiple power domains in a mixed signal environment
• Strong scripting skills (ideally Python) and a working knowledge of automation, version management and continuous integration techniques
• Excellent communication and interpersonal skills
• Excellent time management and organisational skills
• Ability to inspire and empower others to deliver high quality IP within tight schedules

Even better if you have:

• Experience of emulator and FPGA platforms
• UPF and low power/ multiple power domain experience, particularly in a mixed signal environment
• DFT & ATPG experience
• Development of mixed signal IP