About the Job
- Hands-on experience with employing constrained-random coverage driven verification methodology using UVM.
- Working with the design team to validate and verify any requested design changes throughout the project life cycle.
- Develop test plan from specification and architect system-level verification environments
- Develop test-bench components, and coverage metrics
- Execute RTL/Gate level simulations and analyze results
- Work with the mixed-signal team on the co-simulation and verification of mixed-signal IPs
- Contribute to design/verification process automation
- B.Sc. in Electronics/Computer Engineering
- Years of experience in the same field: 0-4 Years of experience in developing SV-based verification environments
- English Language Proficiency: Fluency
- Computer skills required: Unix/Linux operating system
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
- Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
- Familiarity with RTL design, synthesis, and CDC analysis is a plus
- Working knowledge of shell, Perl, and TCL scripting is a plus
Apply for job
To view the job application please visit mixel.com.