Full Job Description
- Experience in complex SOC-level DFT execution in advanced finFET technology.
- BSEE or MSEE with at least 2+ years of DFT experience in high-complexity SoC designs.
- Strong DFT fundamental knowledge from defective models to ATPG algorithm
- Deep knowledge of EDA tools such as Synopsys Tetramax or Mentor Tessent
- Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes.
- Must possess good communication skills, be self-driven, and be a good team player.
Education: Bachelor’s (Preferred)
Experience: 2 years (Preferred)
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