Design Verification Engineer
Website Andes Technology
Available for either Senior or Mid Level
Role
This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily activity includes:
- Communication with peers to discuss technical details
- Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
- Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
- Hands-on verification work including verification regression management, debugging and bug-reports
- Provide technical guidance to junior members of the team
- Technical documentation
Technical Requirements
- Bachelor’s or Master’s degree in related engineering field
- Strong communication skills
- Experience using Verilog, System Verilog
- Strong mastery using Unix and scripting languages such as make, shell, perl or python
Desirable Skills
- Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
- Experience coding in assembly languages
- Experience in UVM, formal, coverage grading, coverage analysis, bug tracking
Patience and good leadership skills - Strong desire to learn and willing to devote extra effort to achieve perfection
- Strong team player and possess a positive attitude
SPIE Monterey- ASML, INTC – High NA Readiness- Bigger Masks/Smaller Features