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Design Verification Engineer

Design Verification Engineer
by Admin on 07-08-2022 at 1:53 pm

Website Alphawave Semi

What You’ll Do

  • Build system-Verilog test benches and writing test cases for verifying high-speed Serdes design.
  • Working with design team to define and implement functional test plans and analysis coverage reports.
  • Setup daily regression, analyze results and tracking progress.
  • Develop digital DSP models for RTL matching.
  • Setup gate-level simulation and assist power analysis.
  • Support post-silicon bring-up activities.
  • Support IP releases and IP integration.

What You’ll Need

  • Must have extensive experience in developing UVM testcases.
  • Constrained-random verification and formal verification.
  • Working knowledge of DSP and Experience in mixed-signal verification.
  • Python, Perl, C/C++, GNU make, Verilog/system-Verilog.
  • Strong written and verbal communication skills. Enjoy collaborating with peers and contribute to a team-oriented work environment.

About You

  • Extremely detail oriented
  • Great collaboration and communication skills
  • Superb analytical and problem-solving skills
  • Customer focused attitude
  • Drives for consistency
  • Takes personal pride in high standard of outputs
  • Self-motivated and self-managing
  • Able to adapt to fast moving, changing environment
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