PCIe Webinar Banner

Design Engineer – Mid or Senior level

Design Engineer – Mid or Senior level
by Admin on 11-08-2023 at 8:07 pm

Website Andes Technology


This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the chance to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.

As a member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.

Daily activity includes:

  • Communication with peers to discuss technical details
  • Competitive analysis and critique pros and cons, such as the balance of performance, area, power
  • Explicit CPU hardware design ranging such as fetch units, scheduling, complex vector or floating-point maths, load-store units, coherent memory access or multi-core debug architecture
  • Design quality analysis including synthesis to assess frequency, area, power quality
  • Providing technical guidance to junior members of the team
  • Technical documentation

Technical Requirements

  • Over 3 years for Mid level/10 years for Senior level of applicable work experience
  • Bachelor’s or Master’s degree in related engineering field
  • Strong communication skills
  • Experience in bus protocols such as AXI, CHI
  • Experience of ASIC design techniques, pipelines and basic CPU microarchitecture
  • Experience in synthesis, physical layout concepts, static timing analysis, clock domain crossing
  • Strong mastery using Verilog, System Verilog
  • Strong mastery using Unix and scripting languages such as make, shell, perl or python

Additional Technical Requirements for Senior Level:

Experience of advanced CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug) and assembly languages

Desirable Skills

  • Patience and good leadership skills
  • Strong desire to learn and willing to devote extra effort to achieve perfection
  • Strong team player and possess a positive attitude
  • Experience or knowledge in verification techniques such as UVM, formal, coverage analysis, bug tracking
Share this post via: