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Design Engineer II

Design Engineer II
by Admin on 12-09-2022 at 2:07 pm

Website Cadence

As a Verification Engineer for Memory Controller development team you will contribute to the functional verification of the Cadence’s Memory Controller IP. This person will work with the existing functional verification environment to add new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, and functional and code coverage. Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics.

The position is based in Austin

Position Requirements:

  • BS/MS – Electrical / Computer Engineering
  • SV and UVM fundamentals are required.
  • Exposure to Verification techniques as part of the internship.
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