- Processor core and subsystem microarchitecture and design.
- Actively participate in design, architecture and verification reviews.
- RTL design and synthesis to analyze & optimize power, speed and area of physical implementation.
- Define, maintain and enhance Block level verification environments using latest flows.
- Develop and support reusable design and verification infrastructure using scripting tools.
- Write technical design documents.
- Strong understanding of processor architectures, instruction set including DSPs, ASIC/SOC/FPGA design and verification flow including RTL design, verification, logic synthesis and timing analysis.
- Familiarity or experience with cache memory systems, bus interfaces, and peripherals like DMA, I2S, SPI, PDM.
- Knowledge or experience in Verilog, SytemVerilog, design compiler, scripting tools (python/perl), verification tools, physical design implementation flow with Synopsys tools.
- Programming skills in C/C++/System C/Assembly.
- Master’s degree or higher in Electrical Engineering.
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