SemiWiki Podcast Banner

DDR PHY Logic Design Engineer

DDR PHY Logic Design Engineer
by Admin on 06-02-2022 at 3:25 pm


The Mixed Signal IP Solutions Group (MIG) within the IP Engineering Group is looking for a Logic Design Engineer. You will work on high-speed digital design and is targeted towards low power optimized implementations of high speed IPs.

Responsibilities of the role include, although not limited to:

  • Implementing RTL in System Verilog, validating the design, synthesizing the design and closing timing.
  • You will also have an opportunity to work on high-level understanding of the architecture through to the details of timing.
  • You will contribute to specifications at multiple levels, including the HAS and MAS (microarchitecture spec).
  • Balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.

In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills.
  • Solid verbal/written communication skills.
  • Effective team player with continuous learning mindset.
  • Willingness to balance multiple tasks.
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process.
  • Willingness to work with cross-functional teams analytic and debugging skills.


Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Bachelor’s degree in Electrical/Computer Engineering with 4+ years of industry experience.


Master’s degree in Electrical/Computer Engineering with 3+ years of industry experience with:

  • RTL development in System Verilog.
  • Microarchitectural spec development of new features/functionality, including trade-offs and documentation.
  • Low power design with multiple power domains.

Preferred Qualifications:
Experience in:

  • Simulation and debug, using VCS/Verdi/QuestaSim.
  • DDR/LPDDR technologies.
  • Synthesis and Speedpath debug, including false path and multi-cycle path analysis and power, area, and performance trade-offs.
  • Analog design concerns and driving to an optimal solution between analog and digital designs.
  • Debugging mixed signal validation.
  • Post-silicon debug.
  • Development of schedules/timelines for design development.
Apply for job

To view the job application please visit

Share this post via: