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Principal SERDES Design Engineer

Principal SERDES Design Engineer
by Daniel Nenni on 08-10-2020 at 8:35 pm

Website Cadence

Position Description:
This is an opportunity to join a dynamic and growing team of experienced engineers developing physical IP for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly-motivated self-starter who is able to work independently to complete assigned tasks. It is expected that the candidate will contribute to all aspects of mixed-signal design, verification and testing. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure.

Position Requirements:

Deep knowledge of analog/RF CMOS design
Able to create Verilog-A/AMS behavioral models in Cadence
Solid understanding of clocking, data recovery and analog equalization in high-speed systems
Understanding of Modulation techniques such as NRZ/PAM4 SERDES
Good experience with signal integrity and on chip and package issues
Experience with mixed-signal design flow using Cadence
Strong written and verbal communication skills
Familiarity the following items is a plus:

Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
Use of electromagnetic simulations tools
MATLAB or C to facilitate architecture development
Scripting languages such as Perl or Python for automation
Silicon validation testing knowledge and experience
Other requirements:

Excellent verbal and written communication skills
PhD EE degree with 3+ years   design or MS EE with 5+ years of analog design industry experience in advanced process technologies
US Citizen or Permanent resident

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To view the job application please visit cadence.wd1.myworkdayjobs.com.