ASIC Physical Design Engr, I
Website Synopsys
Responsibilities:
- Should be strong in technical concepts, fundamentals, and good team player.
- The role involves daily technical interaction with local, US counter parts.
- Will be part of SNPS IP implementation team and responsible for the implementation and integration of world class D2D,HBI IPs at the cutting edge technology nodes (14nm,10nm and below).
- Timing closure above ~2GHz, mixed signal had macro IP integration,
- Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job.
- Prior working knowledge in the memory interface timing closure, implementation would be an added advantage.
Skills Requirements:
- This role is for a technical ladder and so it requires hands-on working knowledge preferably with SNPS tools like DC, PT, PT-SI and ICC2.
- Typically requires 0-2 years of experience after graduation from a reputed university.
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