ASIC Digital Verification Engr, Sr Staff

Job Description and Requirements

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Senior Staff Verification Engineer

Responsible for the development of functional verification solutions for the IP to ensure right first-time silicon. You will work with our global based verification team of architects and designers to specify requirements and follow through on the implementation. You will help develop interface IP solutions for High Bandwidth Memory (HBM) interfaces.

Responsibilities:

• Understanding Standard Specifications, functional specifications and feature enhancements for the product to create and execute detailed verification plans for the HBM IP Memory cores
• Drive and contribute to technical reviews
• Deploy test bench infrastructure and creation of test cases
• Solve complex / abstract problems
• Take the role of technical head for the Test Environment and achieve high quality verification with a small team of verification engineers
• The role offers ample scope to mentor junior engineers to enhance ones’ leadership skills

Preferred Experience:

• The ability to work autonomously and to drive innovation
• Proficient in SystemVerilog and UVM
• Object oriented coding and verification solutions for productivity, performance, and throughput
• Experience with assertion verification, coverage analysis and System Verilog for protocol-oriented performance analysis and debug
• Programming skills: C, System Verilog, TCL, Python & Perl

Key Qualifications

• BSEE with 15+ years of relevant experience in Electrical Engineering or Computer Engineering or other relevant field of study