- Independently work on the design of ASIC functional blocks in terms of requirement analysis, architecture definition, block design, RTL coding, logic synthesis, andtiming analysis (STA).
- Perform logic synthesis and timing analysis of chips and sub blocks, as well as DFT RTL coding, scan chain/MBIST/boundary scan circuits insertion, and test pattern generation and simulation.
- Work closely with system engineers, physical implementation designers, and testing engineers to complete functional verification, flo orplan design, timing optimization/closure, and DFT ATE testing.
- Master’s or above degree in EE/CS related majors, working experience is unlimited.
- Familiar with RTL coding/UVM (Verilog/System Verilog).
- Familiar with the ASIC design flow, including specification, architecture definition, RTL coding, verification，and synthesis.
- Adept at EDA tools (Synopsys or Cadence), such as VCS, Xcelium, DC, and PT.
- Familiar with C/C++, Perl, Python, or other programming language.
- Knowledge of processor design (ARM or RISC-V) and SOC on-chip bus protocols(AMBA/NOC) is a plus.
- Knowledge of audio and video interfaces such as MIPI/HDMI/DP/SPDIF/I2S is a plus.
- Knowledge of interfaces such as USB/PCIe/Ethernet/DDR/SD/eMMC/SPI/CAN is a plus.
- Knowledge of processor (GPU/CPU) or computer architecture, AI, ISP, or video processing is a plus.
- Self-motivated and a good team player. Good communication skills in both Chinese and English in either listening, speaking, reading or writing.
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To view the job application please visit www.verisilicon.com.