ASIC Design Engineer, Senior Staff

What You’ll Do          

• Having knowledge of PCIe, CXL, Ethernet, OTN and UCIe will be an asset
• Contribute to RTL design, architecture and specifications of the ASICs, FPGAs and IP blocks
• Verify, debug and help productize ASICs, FPGAs and IP blocks
• Assist DV engineers in developing and executing individual test-cases against the RTL if needed
• Assist DV engineers in architecting verification and test infrastructure for highly complex ASIC and SoC designs using the latest simulation and debugging tools if needed
• Contribute to the development and documentation of the verification plan
• Working with our external customers and/or internal engineers to verify, validate and deliver their designs for use in OTN / Ethernet FPGAs or ASICs
• Mentor junior engineers

What You’ll Need

• BS, MS or PhD in Electrical Engineering, Computer Science and/or equivalent
• MSEE with 5 year of experience or BSEE with 7 years of experience in ASIC or FPGA development
• Have the knowledge of telecommunications protocol (OTN transport systems, Ethernet, CXL, PCIE etc)
• Solid experience in RTL coding VHDL, Verilog and System Verilog
• Experience in System Verilog + UVM
• Experience with FPGA compilation tools
• Experience with design and verification tools like Vivado/Quartus
• Excellent ability to use Randomised and Directed Verification Methodologies
• Experience with Unix/Linux Shell scripting
• Experience with source code revisioning systems, e.g. SVN, CVS, RCS
• Experience with PERL, TCL, Python, and C/C++ programming, an asset

About You

• Excellent communication skills
• Able to listen to and appreciate ideas and opinions that differ from yours
• Extremely detail oriented
• Superb analytical and problem-solving skills
• Drives for consistency
• Takes personal pride in high standard of outputs
• Self-motivated and self-managing
• Mentoring and coaching skills