Job Description and Requirements
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
What you will learn:
This internship is with our Solutions group to start in May or June 2020 for up to 3 months.
In this role, you will be responsible for learning management of DDR, PCIe and other protocols. The primary focus will be on high speed SOC/ASIC interconnects, its applications and developing comprehensive training for internal consumption. We are looking for a SoC and protocols intern with a passion to develop and document the latest technologies.
- Experience with ASIC flow and RTL – System Verilog or Verilog.
- Proficient with C/C++, UNIX, HDL (Verilog/VHDL) and has a strong understanding of ASIC design flow, VLSI, and/or CAD engineering
- Protocol experience in AMBA, PCIe, DDR and/or Ethernet
- Excellent written and verbal communication, excellent organization skills, and highly self-motivated.
- HW Design experience with AXI, AHB, PCIe, Ethernet and/or DDR.
- Protocol verification experience on UVM environment, with VIP.
MS or PhD candidate in EE/ECE
Apply for job
To view the job application please visit sjobs.brassring.com.