Job Title: Physical Design (PD) Hardware Engineer
Location: Campbell, CA
Organization: Arteris IP
Date posted: 2020-03-09
Arteris IP is looking for an experienced PD Hardware Engineer who wants to contribute to the backbone of some of the world’s most popular SoCs. You will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the word’s most sophisticated mobile, telecom, automotive, and consumer SoC designs. You’ll go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be a part of a proven-successful start-up, and to influence development environment, architecture, verification, and everything in-between – you’ll no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.
You are the kind of person that brings intelligence, motivation, and sense of humor to the office
You have 3 plus years of experience in ASIC/SoC back end design
You have in-depth knowledge of physical design constraints for multi clock and multi power domain designs
You have in-depth knowledge of running synthesis and creating floor plans based on data flow
You understand the complete tool-flow from RTL to netlist
You have worked with Synopsys back end tools
You have gone through the complete flow from RTL to GDS at 16nm or below and delivered a successful SoC
You are excited about using software to accelerate RTL design and back end design
You have experience with scripting languages such as TCL/Perl/Python etc.
You have experience with automation of back end flows
You have experience with SRAM compilers
You have worked with Cadence back end tools
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To view the job application please visit www.arteris.com.