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Principal Verification Engineer

Principal Verification Engineer
by Daniel Nenni on 08-01-2020 at 8:05 pm

  • Full Time
  • San Jose, CA
  • Applications have closed

Arm processors are the brains in billions of diverse electronic devices. Our CPU group defines, designs, and validates all of Arm’s processor IP and collaborates with the world’s leading technology companies. As an engineer in the Chandler, Arizona-based CPU Verification team, you will join a talented team responsible for verification of the next-generation Arm Cortex-A class CPU design. In this role, you will help to enable the team of talented verification engineers to perform their responsibilities more efficiently. The job focuses on the development of tools and improving the work flows used by the CPU engineering team.

What will I be accountable for?

Working closely with the Verification and RTL design team to identify the opportunities for improvements to the current simulation verification methodologies
Developing and improving the architecture of SystemVerilog/UVM test benches for functional verification of CPU and its components
Working with EDA vendors to introduce the new verification aids and help to improve the performance of already deployed tools
Develop new and improve existing internal tools and work flows to maximize the efficiency of simulation verification-based activities including debug and coverage.
Working closely with other engineering and services teams within ARM to help them adopt the best solutions

Job Requirements
What skills, experience, and qualifications do I need?

MS or BS in Computer Science, Electrical Engineering, or Computer Engineering
Minimum of 15 years of CPU verification experience
High-level understanding of CPU architecture and microarchitecture, including experience in the area of out-of-order microarchitecture and/or coherent memory systems
Strong software engineering skills including understanding of object-oriented programming, data structures, and algorithms
Experience with SystemVerilog/UVM test benches and IP verification technologies
What would give my candidacy an edge?

Experience architecting SystemVerilog/UVM test benches with focus on usage efficiency, performance, debuggability, and reusability
Strong knowledge of object-oriented programming, scripting languages, and software development technologies
Experience developing software tools and work flows in distributed computing systems
CPU microarchitecture including knowledge of out-of-order execution and/or CPU memory system microarchitecture experience

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